This invention relates to a circuit for detecting voltage input level changes or bit signal transitions at the terminals of integrated circuit logic arrays.
Previously available circuits for detection of such input or address transitions have required separate supply voltage sources to drive width control circuitry, have been unreliable when sensing transitions from a large number of address inputs, have required circuit elements other than complementary metal oxide semiconductor (CMOS) devices, and have consumed relatively large amounts of power. Accordingly, there is a need for an address detection circuit that eliminates the foregoing disadvantages of prior art circuits.